1. Field of the Invention
The present invention relates to a processing method for high-frequency transmission applications, more particularly, to an output circuit for high-frequency transmission applications, which can avoid the errors of a first set of transmitted data caused by the circuitry factor.
2. Description of the Related Art
Due to the high-speed requirements of electronic systems, the data transmission speed must be raised to meet the needs of the system. There are many techniques for increasing the transmission speed. For example, the double data rate technique, namely, DDR, can be used in synchronized dynamic random access memories (SDRAM) to speed up the original transmission speed. This technique utilizes both the rising edge and the falling edge within a clock signal to acquire double the original data rate under the same timing specification.
FIG. 1 (PRIOR ART) is a sampling timing diagram illustrating the operating principle of the DDR technique. As shown in the figure, sampling clocks STROB and STROB# are complementary pulse signals with a fixed frequency. In addition, the edges of the sampling clocks STROB/STROB# are also opposite, that is, one is the falling edge and the other is the rising edge. For example, at time points S1 and S3, the sampling clock STROB is on the falling edge and the sampling clock STROB# is on the rising edge. At time point S2, the sampling clock STROB is on the rising edge and the sampling pulse STROB# is on the falling edge. Therefore, data on the data signal DATA can be sampled based on these time points S1, S2 and S3. Accordingly, the practical data rate over a transmission line can be doubled by using the same sampling clocks.
FIG. 2 (PRIOR ART) is a circuit diagram of the conventional output circuit for the data signal DATA. As shown in the figure, output data A is sent to buffers 10 and 12, and further to the gates of PMOS transistor 14 and NMOS transistor 16 serially connected, respectively. Thus, the data signal DATA is pulled out from the connected drain electrodes of the PMOS transistor 14 and the NMOS transistor 15. When the output data A to be output is at logic HIGH, the NMOS transistor 16 turns on and the PMOS transistor 14 turns off. In this case, the data signal DATA is 0V (the ground voltage), which represents logic xe2x80x9c0xe2x80x9d. When the output data A to be output is at logic LOW, the PMOS transistor 14 turns on and the NMOS transistor 16 turns off, the data signal DATA is the system voltage VPP, which represents logic xe2x80x9c1xe2x80x9d.
FIG. 3 (PRIOR ART) is a circuit diagram of the conventional output circuit for the sampling clocks STROB/STROB#. Notice that FIG. 3 only demonstrates an output circuit for one of the sampling clocks STROB/STROB# and the output circuits for both of the sampling clocks STROB/STROB# are similar. As shown in the figure, control signals S/S# are sent to buffers 20 and 22, and further to the gates of PMOS transistor 24 and NMOS transistor 26 serially connectedly, respectively. The corresponding sampling clocks STROB/STROB# are pulled out from the connected drain electrodes of the PMOS transistor 24 and the NMOS transistor 26. The signal variations of the sampling clocks STROB/STROB# depend on the control signals S/S#.
However, since the high-frequency data will be affected by the delay effect or other factors during the transmission over the transmission line, the sampling clocks STROB/STROB# usually cannot achieve full swing at the first sampling point. If the sampling clocks STROB/STROB# are going to 1.5V and 0V at the first sampling point, respectively, they cannot achieve these predetermined voltages within the timing specification in practical operation. In this case, since the sampling operation is also affected by other factors, for example, ground/power bounce, IR drop or signal coupling, the extraction of the data signal DATA is probably incorrect.
FIG. 4 (PRIOR ART) is a waveform diagram showing the waveforms of the sampling clocks STROB/STROB# at the first set of data. As shown in the figure, the waveforms of the sampling clocks STROB/STROB# cannot achieve full swing. This could cause the drifting of setup/hold time between the data signal DATA and the sampling clacks STROB/STROB# and the deterioration of the signal eye patttern. As described above, the DDR system extracts data on the data signal DATA based on the opposite crossing point of the sampling clocks STROB/STROB#. Therefore, in the prior art, the extraction of the first set of transmitted data is prone to error.
Accordingly, an object of the present invention is to provide an output circuit, which can prevent the first set of the transmitted data from being erroneous in high-frequency transmission applications and is especially suitable for transmission systems with the DDR function.
According to the above object, the present invention provides an output circuit, which can output a sampling clock signal, for example, one of the sampling clock signals in the double data rate system. The output terminal of the output circuit is initially set as a first logic level (such as logic xe2x80x9c1xe2x80x9d). The output circuit includes an output transistor unit having an input terminal and an output terminal serving as the output terminal of the output circuit. In addition, there is a pre-pulled unit, which is connected between the output terminal of the output circuit and a second logic level and receives a control signal. There is a pulse in the control signal before the first time the logic level starts to change at the output terminal of the output transistor unit. This pulse can be used to control the pre-pulled unit, so that the output terminal of the output circuit shifts by a voltage difference toward the second logic level from the initial first logic level. For example, the first logic level corresponds to logic xe2x80x9c1xe2x80x9d. Before the sampling clock signal falls from logic xe2x80x9c1xe2x80x9d to logic xe2x80x9c0xe2x80x9d for the first time, the control signal can control the pre-pulled unit to lower the voltage of the original logic xe2x80x9c1xe2x80x9d, thereby guaranteeing the pulse signal correctly falling down to logic xe2x80x9c0xe2x80x9d at the first conversion time. The above operation also can be applied to the case where the logic xe2x80x9c0xe2x80x9d rises to logic xe2x80x9c1xe2x80x9d.
In addition, the input terminal of the output transistor unit can be connected to a transmission gate unit, which is used to transmit an input signal to the input terminal of the output transistor unit. The transmission gate unit can be controlled by the control signal. Normally, the input signal can be sent to the input terminal of the output transistor unit via a first channel in the transmission gate unit. During the period of the pulse of the control signal, the input signal can be sent to the input terminal of the output transistor unit via the second channel in the transmission gate unit. The second channel involves a delay time with respect to the first channel to adjust the timing variation introduced by the previously pulling operation.
Furthermore, the present invention also provides an output apparatus of double data rate system, which includes a plurality of data output circuits for the data signals, a first sampling clock output circuit and a second sampling clock output circuit for outputting the first sampling clock and the second sampling clock, respectively. The data signal can be sampled at the intersections of rising edges and falling edges of the first sampling clock and the second sampling clock, thereby doubling the sampling rate. The first sampling clock output circuit and the second sampling clock output circuit can be implemented by the above-described output circuit. It is noted that the logic value of the first sampling clock is opposite to the logic value of the second sampling clock for the sampling purpose of the double data rate system.